CS250: VLSI Systems Design
Spring 2007

Projects:

Projects can be either individual or in small groups - however, the amount of work and results must be reflective of the extra people.

Ideally, your project will have an element of "analysis" and maybe, but not necessarily, an element of "synthesis" (design). To get a general idea, plan your project in such a way that if things work out you could later turn it into a conference paper.

If already involved in a research project, think about tying your cs250 project to that. This would give you a head-start on tools, partial designs, benchmarks, etc. Also, if you are taking another grad class that requires a project, you might think about doing one project that satisfies both classes. You may need to do extra work, or present it in a different way, but this could save you a lot of time.

If you don't have any ideas for a project, start by looking at the assigned conference papers (not the "survey" papers). These might give you some ideas on a variation or extension to one of the projects described by the authors.

Below as a few project ideas. Most of these are just rough ideas that you would need to think though more carefully and add details.

As a last resort, you can consider doing a "survey" type project. The idea of this would be to take some concept related to the class and find a large number of papers and other information, digest it, summarize it, and write a lengthy summary report on the topic.

Project Ideas (more might be added later)

1. [New from Ivan Sutherland] I will provide the interested student with two pieces of data:
   1. The LAYOUT of several dozen ring oscillators where identical inverters drive different kinds of loads such as several inverters each, a long piece of wire, and so forth.
   2. The measured frequency of each ring oscillator.
   The layouts will be in Electric (layout program). I think the public version will read the files I could provide. If not, we can get a version that will read the files. The frequency numbers are in written form. We have data from several chips. The schematic diagram is not available. (Student will have to deduce it from the layout - not a hard task because it's just a set of ring oscillators. The task is to characterize the technology. The student will need to garner as much information as possible about the technology parameters as the rings provide. To get results the student will have to think though what each ring measures and draw suitable conclusions. I'm sure I can provide these data for MOSIS 180 nm process. I may be able to provide them in TSMC 90 nm process. Depends on how proprietary the TSMC people are. I might also be able to provide a chip. That depends on whether we can find one and what else is on it. The educational exercise is figuring out from the layout what causes the ring to operate at a different frequency. Turning that into quantitative values requires a little algebra.

2. Similar to the Rose paper, do a study on a set of circuits comparing FPGA implementation to ASIC implementation. Consider Xilinx FPGAs instead of Altera. Consider a different benchmark set.

3. [Lazzaro] Given the low-power circuit style in the Wang and Anantha paper, how would you optimize the process for power (choosing the Vt's, after coming up with a model for how Vt affects the Vgs=0 currents, and then reoptimizing Vdd once you're done). There are a few other things you could do with that paper, like try to evaluate the impact of a full-custom vs standard-cell layout, given the architecture, etc.

4. [Lazzaro] Given the Niagara and Niagara II designs as a starting point, do analysis to justify their major architecture decisions with respect to power -- L1 and L2 cache characteristics, number of pipeline stages, multithreading style, etc.

5. Using a real FPGA (on a development board) do experiments to determine the range of successful operation for varying Vdd. Measure the resulting power consumption. Explain the results.

6. Asynchronous circuit study. Use GasP ore some other asynchronous circuit style and design some familiar function (array multiplier, for instance). Simulate the results and compare in performance, power, and area to a synchronous design.

7. Based on GARP, do an analysis of a its size, performance, and power in a modern IC process. Hand-map new conputational kernels.

8. [Lazzaro] Do a study on how to design an FPGA fabric on existing FPGA chips, as I brought up in class. How can we trade off designing the new architecture to be efficiently realized on existing FPGAs, while also designing the new architecture to be a good target for the sorts of applications people would want to run on a "virtual FPGA" (like reconfigurable apps)?

9. [Lazzaro] Using the 200 mV multiplier paper as a starting point, sketch out the design of a 200 mV microprocessor, whose design point is 10 years of life on a small battery, and whose application domain is implantable devices (pacemakers, etc). The big challenge is, how can we spread out the CPU is space to get the parallelism we will need to overcome the very slow clock speeds. Both ISA-level parallelism (i.e. look at options like VLIW) and logic-design innovation (find new ways to spread out ALUs deeply in space, given this unusual design point).

10. [Lazzaro] The rebirth of PLAs to replace standard cells for control logic in a "radically simplified design rule" world. The goal here is to take some time to study just what kind of layout restrictions currently exist and will exist in the future to make resolution-enhanced lithography work, and then revisit PLAs and other regular structures to see if their layout-friendliness can overcome their logic depth limitations.

11. [Lazzaro] Revisiting bit-serial in an FPGA world. Start with the body of work on bit-serial architectures, ask, how can these architectures be modified to work optimally in an FPGA. Ideally, the "hardwired logic" in each LUT (carry chains) and the dedicated resources in the FPGA (multiplier arrays, etc) would be put to use in a clever way.