Publications | John Wawrzynek

Pending Publication

Chen Chang, John Wawrzynek, Robert W. Brodersen. "A High-End Reconfigurable Computing System and Design Environment," invited paper, IEEE MICRO, Spring 2006.

Zohair Hyder, John Wawrzynek. "Defect Tolerance in Multiple-FPGA Systems," invited paper, IEE Proceedings - Computers & Digital Techniques, Summer 2006.

Andre DeHon, Randy Huang, and John Wawrzynek. "Stochastic Spatial Routing for Reconfigurable Networks," submitted to Journal of Microprocessors and Microsystems: Special Issue on FPGA-Based Reconfigureable Computing.

DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek. "Stream Computations Organized for Reconfigurable Execution," submitted to Journal of Microprocessors and Microsystems: Special Issue on FPGA-Based Reconfigureable Computing.

Journals and Conferences

Chen Chang, John Wawrzynek, Robert W. Brodersen. "Design & Application of BEE2 - a High-end Reconfigurable Computing System," HotChips 17, A Symposium on High Performance Chips, Aug 14-16, 2005.

C. Chang, J. Wawrzynek, R. W. Brodersen, "The Design and Application of a High-End Reconfigurable Computer System," Proceedings of the 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA2005), pp. 129-136, June 2005.

Z. Hyder and J. Wawrzynek. "Defect Tolerance in Multiple-FPGA Systems," Proceedings of IEEE 15th International Conference on Field Programmable Logic and Applications (FPL2005), Aug 24--26, 2005. Best Paper Award

C. Chang, J. Wawrzynek, and R. W. Brodersen. "BEE2: A High-End Reconfigurable Computing System," IEEE Design and Test of Computers, 22(2):114--125, Mar/Apr 2005.

Lazzaro, J. P., Wawrzynek, J. "An RTP Payload Format for MIDI." The 117th Convention of the Audio Engineering Society (AES), October 28-31, 2004, San Francisco, CA, USA.

Nicholas Weaver, John Hauser, and John Wawrzynek, "The SFRA: A Corner-Turn FPGA Architecture", the 12th ACM International Symposium on Field Programmable Gate Arrays (FPGA), February 2004.

J. Yeh and J. Wawrzynek. "Compute-Resource Allocation for Motion Estimation in Real-Time Video Compression," Asilomar Conference on Signals, Systems, and Computers, November 2003.

Joseph Yeh and John Wawrzynek. "Quality Based Compute-Resource Allocation in Real-time Signal Processing," Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 03), Apr 6-10, 2003.

Nicholas Weaver, Yury Markovskiy, Yatish Patel, and John Wawrzynek. "Post Placement C-slow Retiming for the Xilinx Virtex FPGA," Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA 2003) February 23--25, 2003.

Randy Huang, John Wawrzynek, and Andre DeHon. "Stochastic, Spatial Routing for Hypergraphs, Trees, and Meshes," Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA 2003) February 23-25, 2003.

Y. Markovskiy, E. Caspi, R. Huang, J. Yeh, M. Chu, J. Wawrzynek, and A. DeHon. "Analysis of Quasi-Static Scheduling Techniques in a Virtualized Reconfigurable Machine," Proceedings of the Tenth ACM International Symposium on Field-Programmable Gate Arrays (FPGA 2002) Feb. 24-26, 2002.

A. DeHon, R. Huang, and J. Wawrzynek. "Hardware-Assisted Fast Routing," Proceedings of the IEEE Symposium on Field-Programmable Gate Arrays for Custom Computing Machines (FCCM2002) , April 22-24, 2002.

E. Caspi, R. Huang, Y. Markovskiy, J. Yeh, J. Wawrzynek, and A. DeHon. "A Streaming Multi-Threaded Model," Third Workshop on Media and Stream Processors (MSP-3) , December 2, 2001.

J. P. Lazzaro and J. Wawrzynek. "A Case for Network Musical Performance." The 11th International Workshop on Network and Operating Systems Support for Digital Audio and Video (NOSSDAV 2001), June 25-27, 2001, Port Jefferson, New York.

J. P. Lazzaro and J. Wawrzynek. "Compiling MPEG 4 Structured Audio into C." Proceedings of the Second IEEE MPEG-4 Workshop and Exhibition (WEMP) June 18-20, 2001, San Jose, CA.

T. Callahan and J. Wawrzynek. "Adapting Software Pipelining for Reconfigurable Computing," Published in Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES2000) , November 17-18, 2000.

E. Caspi, M. Chu, R. Huang, J. Yeh, J. Wawrzynek, and A. DeHon "Stream Computations Organized for Reconfigurable Execution (SCORE)," appearing in Conference on Field Programmable Logic and Applications (FPL 2000, August 28--30, 2000).

N. Weaver and J. Wawrzynek. "A Comparison of the AES Candidates Ameanability to FPGA Implementation," Proceeding of the Third Advanced Encryption Standard Candidate Conference, (April 13-14, 2000) http://csrc.nist.gov/encryption/aes/round2/conf3/papers/AES3Proceedings.pdf

T. Callahan, J. Hauser, and J. Wawrzynek. "The Garp Architecture and C Compiler," IEEE Computer, April 2000.

A. DeHon and J. Wawrzynek. "Reconfigurable Computing: What, Why, and Design Automation Requirements?" Proceedings of the 1999 Design Automation Conference (DAC 1999, June 21-25, 1999)

S. Perissakis, Yangsung Joo, Jinhong Ahn, A. DeHon, and J. Wawrzynek. "Embedded DRAM for a Reconfigurable Array." Proceedings of the 1999 Symposium on VLSI Circuits (VLSI 1999, June 17-19, 1999).

T. Hodes, J. Hauser, A. Freed, J. Wawrzynek, and D. Wessel, "A Fixed-Point Recursive Digital Oscillator for Additive Synthesis of Audio," Proc. IEEE Int. Conf. Acoustics, Speech, and Signal Processing, Phoenix, AZ, March 1999.

W. Tsu, K. Macy, A. Joshi, R. Huang, J. Wawrzynek, et al., "HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array," AGM/SIGDA Int. Symp. Field Programmable Gate Arrays, Monterey, CA, February 1999.

J. Lazzaro and J. Wawrzynek, "JPEG Quality Transcoding Using Neural Networks Trained with a Perceptual Error Measure," Neural Computation, Vol. 11, No. 1, January 1999.

T. J. Callahan and J. Wawrzynek, "Instruction-level Parallelism for Reconfigurable Computing," Proc. Int. Workshop Field-Programmable Logic and Applications, from FPGAs to Computing Paradigm, Tallinn, Estonia, August-September 1998.

T. Callahan, P. Chong, A. DeHon, and J. Wawrzynek. Fast Module Mapping and Placement for Datapaths in FPGAs." Published in Proc. of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays (FPGA 1998), February 22-24, 1998.

M. Chu, N. Weaver, K. Sulimma, A. DeHon, and J. Wawrzynek. "Object Oriented Circuit-Generators in Java." Published in Proc. of the International Symposium on Field-Programmable Gate Arrays for Custom Computing Machines (FCCM 1998), April 15-17, 1998.

J. Lazzaro, J. Wawrzynek, and R. P. Lippmann. A Micropower Analog Circuit Implementation of Hidden Markov Model State Decoding. IEEE Journal Solid State Circuits 32:8, 1200-1209, August 1997.

J. R. Hauser and J. Wawrzynek. Garp: A MIPS Processor with a Reconfigurable Coprocessor, In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 97, April 16-18, 1997), pp. 24-33.

J. Lazzaro and J. Wawrzynek. Speech Recognition Experiments with Silicon Auditory Models. Analog Integrated Circuits and Signal Processing An International Journal, 13:1-2. 37-51, 1997.

J. Lazzaro, J. Wawrzynek, and R. Lippmann. A Micropower Analog VLSI HMM State Decoder for Wordspotting, in Advances in Neural Information Processing Systems 9 (NIPS96), Proceedings of the 1996 Conference, M. C. Mozer, M. Jordan, and T. Petsche, Eds., Cambridge, Mass: MIT Press, (1996).

K. Asanovic, J. Beck, B. Irissou, B. Kingsbury, and J. Wawrzynek. T0: A Single-Chip Vector Microprocessor with Reconfigurable Pipelines. Proceedings of the 22nd European Solid-State Circuits Conference, September 1996, pp. 344-347.

J. Wawrzynek, K. Asanovic, B. Kingsbury, J. Beck, D. Johnson, and N. Morgan. SPERT-II: A Vector Microprocessor System. IEEE Computer, March 1996.

T. Callahan and J. Wawrzynek. A Simple Profiling System for SUIF, The First SUIF Compiler Workshop, Stanford University, January 1996.

Krste Asanovic, James Beck, Bertrand Irissou, Brian E. D. Kingsbury, Nelson Morgan, and John Wawrzynek. The T0 Vector Microprocessor. In Proceedings of Hot Chips VII, August 1995.

J. Lazzaro and J. Wawrzynek. Silicon Models for Auditory Scene Analysis. In Michael Hasselmo, David Touretzky, and Michael Mozer, editors, Advances in Neural Information Processing Systems5 (NIPS95), Proceedings of the 1995 Conference. MIT Press, December 1995.

J. Wawrzynek, K. Asanovic, B. Kingsbury, J. Beck, D. Johnson, and N. Morgan. SPERT-II: A Vector Microprocessor System and its Application to Large Problems in Backpropagation Training. In Michael Hasselmo, David Touretzky, and Michael Mozer, editors, Advances in Neural Information Processing Systems5 (NIPS95), Proceedings of the 1995 Conference. MIT Press, December 1995.

J. Lazzaro and J. Wawrzynek. A Multi-Sender Asynchrounous Extension to the AER Protocol. In 1995 Conference on Advanced Research in VLSI. IEEE Computer Society, 1995.

K. Asanovic, J. Beck, J. Feldman, N. Morgan, and J. Wawrzynek. A Supercomputer for Neural Computation. In Proceedings of the International Conference on Neural Networks, volume 1, pages 5-9, 1994.

J. Lazzaro, J. Wawrzynek, and A. Kramer. Systems Technologies for Silicon Auditory Models. IEEE Micro, 14(3):7-15, June 1994.

K. Asanovic, J. Beck, J. Feldman, N. Morgan, and J. Wawrzynek. Designing a Connectionist Network Supercomputer. International Journal of Neural Systems, 4(4):317-326, December 1993.

J. Wawrzynek, K. Asanovic, and N. Morgan. The Design of a Neuro-Microprocessor. IEEE Journal on Neural Networks, 4(3), 1993.

J. Lazzaro, J. Wawrzynek, M. Mahowald, M. Sivilotti, and D. Gillespie. Silicon Auditory Processors as Computer Peripherals. IEEE Journal on Neural Networks, 4(3):523-528, 1993.

K. Asanovic, J. Beck, J. Feldman, N. Morgan, and J. Wawrzynek. Development of a Connectionist Network Supercomputer. In Proceedings of the Third International Conference on Microelectronics for Neural Networks, pages 253-262, Edinburgh, Scotland UK, April 1993. UnivEd Technologies Ltd, University of Edinburgh.

K. Asanovic, N. Morgan, and J. Wawrzynek. Using Simulations of Reduced Precision Arithmetic to Design a Neuro-Microprocessor. Journal of VLSI Signal Processing, 6:33-44, June 1993.

J. Wawrzynek and B. Irissou. High Speed 64-bit CMOS Datapath. In G. Borriello and C. Ebeling, editors, Research on Integrated Systems, Proceedings of the 1993 Symposium, pages 143-154, Seattle, Washington, March 1993. The MIT Press.

J. Lazzaro, J. Wawrzynek, M. Mahowald, M. Sivilotti, and D. Gillespie. Silicon Auditory Processors as Computer Peripherals. In Stephen José Hanson, Jack D. Cowan, and C. Lee Giles, editors, Advances in Neural Information Processing Systems 5, Proceedings of the 1993 Conference, pages 820-827. Morgan Kaufmann Publishers, December 1992.

K. Asanovic, J. Beck, B. Kingsbury, P. Kohn, N. Morgan, and J. Wawrzynek. SPERT: A VLIW/SIMD Microprocessor for Artificial Neural Network Computations. In José Fortes, Edward Lee, and Teresa Ming, editors, Proceedings of the International Conference on Application Specific Array Processors, pages 178-190. IEEE Computer Society Press, August 1992.

K. Asanovic, J. Beck, B. Kingsbury, P. Kohn, N. Morgan, and J. Wawrzynek. SPERT: A VLIW/SIMD Neuro-Microprocessor. In Proceedings of the International Joint Conference on Neural Networks, pages 577-582, 1992.

P. de Dood, J. Wawrzynek, E. Liu, and R. Suaya. A Two-Dimensional Topological Compactor Using Octagonal Geometry. In Proceedings of the 28th ACM/IEEE Design Automation Conference. ACM Press, June 1991.

A. Cassotto, B. Kingbury, and J. Wawrzynek. Using VOV, an Automated Design Manager, in a VLSI Design Course. In Gaetano Borriello, editor, Microelectronic System Education Conference, pages 51-59, July 1991.

D. Culler, A. Sah, K. Schauser, T. von Eicken, and J. Wawrzynek. Fine-grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine. In Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, April 1991.

E. Liu, P. de Dood, R. Suaya, and J. Wawrzynek. A Topological Framework for Compaction and Routing. In Carlo H. Séquin, editor, Proceedings of the 13th Conference on Advanced Research in VLSI, pages 212-228. The MIT press, 1991.

K. Asanovic, B. Kingsbury, N. Morgan, and J. Wawrzynek. A Highly Piplined Architecture for Neural Network Training. In IFIP Workshop on Silicon Architectures for Artificial Neural Networks, November 1990.

J. Wawrzynek and T. von Eicken. VLSI Parallel Processing for Musical Sound Synthesis. In Proceedings of the International Computer Music Conference, Glasgow, Scotland, September 1990.

S. Pointer and J. Wawrzynek. Multimedia Digital Signal Processing Tutoring System. In Proceedings of the International Computer Music Conference, Glasgow, Scotland, September 1990.

D. Wessel, R. Felciano, A. Freed, and J. Wawrzynek. The Center for New Music and Audio Technologies. In Proceedings of the International Computer Music Conference, Ohio State University, November 1989. Invited paper.

J. Wawrzynek and T. von Eicken. MIMIC, A Custom VLSI Parallel Processor for Musical Sound Synthesis. In G. Musgrave and U. Lauther, editors, Proceedings of the IFIP IC10/WG10.5 Working Conference on Very Large Scale Integration, Munich, FRG, August 1989.

Book Chapters

J. P. Lazzaro and J. Wawrzynek. "Substractive Synthesis without Filters," in Audio Anecdotes II, edited by Ken Greenebaum and Ronen Barzel, A.K. Peters, publisher, 2004.

Lazzaro, J. P., Wawrzynek, J., "Speech recognition experiments with silicon auditory models," In Lande, T. S. (ed), Neuromorphic systems engineering : neural networks in silicon. Boston : Kluwer Academic, 1998.

K. Asanovic, J. Beck, B. Kingsbury, N. Morgan, and J. Wawrzynek. Training Neural Networks with SPERT-II, In Parallel Architectures for Artificial Neural Networks, Paradigms and Implementations. N. Sundrarajan and P. Saratchandran, editors, 1998, IEEE Computer Society, pp. 345-364.

J. Lazzaro and J. Wawrzynek. Low-Power Silicon Neuron, Axons, and Synapses. In M. E. Zaghloul, J. Meador, and R. W. Newcomb, editors, Silicon Implementation of Pulse Coded Neural Networks. Kluwer Academic Publishers, 1993.

J. Wawrzynek. VLSI Models for Real-time Music Synthesis. In M. Mathews and J. Pierce, editors, Current Directions in Computer Music Research. MIT Press, 1989.

Technical Reports

Arvind (MIT), Krste Asanovic (MIT), Derek Chiou (UT Austin), James C. Hoe (CMU), Christoforos Kozyrakis (Stanford), Shih-Lien Lu (Intel), Mark Oskin (U Washington), David Patterson (UC Berkeley), Jan Rabaey (UC Berkeley), and John Wawrzynek (UC Berkeley), "RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental Parallel HW/SW Platform," Technical Report UCB//CSD-05-1412, September 2005.

Lazzaro, J. P., Wawrzynek, J. (in progress). RTP Payload Format for MIDI. Standards-track working group item, Audio/Video Transport Group, Internet Engineering Task Force (IETF).

Lazzaro, J. P., Wawrzynek, J. (in progress). An Implementation Guide for MIDI. Working group item, Audio/Video Transport Group, Internet Engineering Task Force (IETF).

Lazzaro, J. P. (in progress). Framing RTP and RTCP Packets over Connection-Oriented Transport. Standards-track working group item, Audio/Video Transport Group, Internet Engineering Task Force (IETF).

K. Asanovic, J. Beck, T. Callahan, J. Feldman, B. Irissou, B. Kingsbury, P. Kohn, J. Lazzaro, N. Morgan, D. Stoutamire, and J. Wawrzynek. CNS-1 Architecture Specification. Technical Report TR-93-021, International Computer Science Institute, April 1993.

B. Kingsbury, K. Asanovic, B. Irissou, N. Morgan, and J. Wawrzynek. Recent work in VLSI elements for digital implementations of Artificial Neural Networks. Technical Report TR-91-074, International Computer Science Institute, 1991.

K. Asanovic, J. Beck, B. Kingsbury, P. Kohn, N. Morgan, and J. Wawrzynek. SPERT: A VLIW/SIMD Microprocessor for Artificial Neural Network Computations. Technical Report TR-91-072, International Computer Science Institute, 1991.

N. Morgan, K. Asanovic, B. Kingsbury, and J. Wawrzynek. Developments in Digital VLSI design for Artificial Neural Networks. Technical Report TR-90-065, International Computer Science Institute, 1990.