The emergence of high capacity reconfigurable devices is igniting a revolution in general-purpose processing. It is now becoming possible to tailor and dedicate functional units and interconnect to take advantage of application dependent dataflow. Early research in this area of reconfigurable computing has shown encouraging results in a number of spot areas including cryptography, signal processing, and searching --- achieving 10-100x computational density and reduced latency over more conventional processor solutions.
The BRASS research project takes a system-level approach to architecting reconfigurable computing devices. We ask:
As a focus point for our research, we are investigating the integration of processors and reconfigurable logic (see Reconfigurable Processor). Our first pass at such an architecture is Garp which combines a MIPS-II processor with a fine-grained FPGA coprocessor on the same die (see Garp and Compiling C to Garp). We are also working on more efficient reconfigurable array designs, techniques to simplify and accelerate the mapping process, and strategies for building reconfigurable applications.
For an overview of configurable computing and why it is interesting, see The Role of RC. Also check out these articles in Business Week, Scientific American and a recent issue of IEEE Computer. For more depth, visit the online materials from the configurable computing course.
We are working with two other research efforts at Berkeley which are exploring complementary architectures on the path to tomorrow's system ICs. The IRAM (Intelligent RAM) research group is investigating the issues involved in integrating a processor and DRAM on the same chip. Pleiades is exploring reconfiguration of coarser-grain, application-specific building blocks with an emphasis on low-power computations.