BRASS Research Group

Garp: Combining a Processor with a Reconfigurable Computing Array

Today's general-purpose processors are highly optimized for executing complex sequences of instructions for a popular set of basic operations. Almost by definition, these processors are good at executing average application workloads. Nevertheless, many algorithms contain critical ``kernels'' whose performance significantly impacts total application performance, and which are unlikely to be perfectly implemented by any processor. Reconfigurable hardware may be better at supporting many such kernels for two reasons: First, reconfigurable hardware is better at implementing functions that happen not to map well to the ``standard'' set of operations. And second, control flow can be hard-coded within the reconfigurable array logic, sidestepping instruction bandwidth bottlenecks and thus providing more potential to exploit parallelism.

The focus of the Garp research is the integration of a reconfigurable computing unit with an ordinary RISC processor to form a single combined processor chip. The goal of the research is to demonstrate a tentative viable architecture that gives a speedup for at least some applications.

Garp Block Diagram
Thumbnail sketch of the first Garp implementation:

Additional sources of information

``Garp: A MIPS Processor with a Reconfigurable Coprocessor,'' by John R. Hauser and John Wawrzynek, published in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97, April 16-18, 1997).

``The Garp Architecture,'' (complete specification) by John R. Hauser.

``Augmenting a Microprocessor with Reconfigurable Hardware. '' John Reid Hauser, Ph.D. Thesis, December 2000.

Related project

Automatic C Compilation for the Garp Chip: Featuring predicated and speculative execution; automatic fully-pipelined loop execution (even with multiple and/or data-dependent exits); automatic utilization of streaming memory queues, plus redundant memory access elimination, utilizing SUIF dependence library; full support of arbitrary pointer accesses from the coprocessor; and intelligent hyperblock formation using profiling information.

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