BRASS Research Group

Garp: A MIPS Processor with a Reconfigurable Coprocessor

Article by John R. Hauser and John Wawrzynek, published in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97, April 16-18, 1997), pp. 24-33 (10 pages).

Abstract: Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.

See also:
``Augmenting a Microprocessor with Reconfigurable Hardware.'' John Reid Hauser, Ph.D. Thesis, December 2000.

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