Balancing Interconnect and Computation in a Reconfigurable Computing Array
(or, why you don't really want 100% LUT utilization)

Article by André DeHon published in Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays (FPGA '99, February 21-23, 1999), 10 pages.

Abstract: FPGA users often view the ability of an FPGA to route designs with high LUT (gate) utilization as a feature, leading them to demand high gate utilization from vendors. We present initial evidence from a hierarchical array design showing that high LUT utilization is not directly correlated with efficient silicon usage. Rather, since interconnect resources consume most of the area on these devices (often 80-90%), we can achieve more area efficient designs by allowing some LUTs to go unused---allowing us to use the dominant resource, interconnect, more efficiently. This extends the "Sea-of-gates" philosophy, familiar to mask programmable gate arrays, to FPGAs. Also introduced in this work is an algorithm for "depopulating" the gates in a hierarchical network to match the limited wiring resources.

Paper

• ACM ACM Digital Library Entry FPGA'99.
• PDF Author's local PDF document, fixedws_fpga99.pdf [1.5 MB].
• gzip'ed PostScript document, fixedws_fpga99.ps.gz [115 kB].
• compress'ed PostScript document, fixedws_fpga99.ps.Z [198 kB].
• PostScript document, fixedws_fpga99.ps [1.3 MB].

Talk Slides

• PowerPoint slides, fixedws_talk_fpga99.ppt [478 kB].
• PostScript slides (2up) fixedws_talk2up_fpga99.ps [2.6 MB].

Poster Slides

• PowerPoint slides, fixedws_poster_fpga99.ppt [557 kB].
• PostScript slides (2up) fixedws_poster2up_fpga99.ps [3.3 MB].