BRASS Research Group

Balancing Computation and Memory in High Capacity Reconfigurable Arrays

Ph.D. Dissertation by Stylianos Perissakis.


Reconfigurable arrays have been used to speed up computational tasks, some times achieving orders of magnitude of improvement either in cost/performance or raw performance. An integral part of such systems is a significant amount of memory, distributed among multiple reconfigurable chips. The current scaling trend of VLSI technology, that allows packing of more and more gates on a single silicon die, tends to throw such architectures out of balance, unless significant amount of memory is integrated on the die, close to the processing elements. Embedded DRAM technology, integration of dynamic RAM with logic circuits on the same chip, offers a unique opportunity to balance the processing and memory resources in large reconfigurable chips.

In this thesis I evaluate the potential of embedded DRAM technology in the context of a reconfigurable architecture. I examine the design space for embedded DRAM macros suitable for reconfigurable architectures and present a point design, the {\em Configurable Memory Block} (CMB) for the {\em Trumpet} FPGA. With the aid of sample application kernels, I evaluate the density, performance and energy advantages of embedded DRAM technology over the conventional technology of small internal SRAM banks and larger external memory. Based on a set of typical applications, I develop a methodology for choosing a cost/performance-optimum design point for reconfigurable architectures similar to Trumpet. I find that FPGAs incorporating embedded DRAM banks can demonstrate high performance and energy efficiency, in addition to the obvious integration benefits resulting from the merging of the processing and memory elements on the same chip.

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