Documents

Slides for DARPA Adaptive Computing Systems PI Meeting (June 23, 1997).
Presented by John Wawrzynek and André Dehon.

``Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial.''
Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, Yury Markovskiy, John Wawrzynek, and André DeHon.
Published in Proceedings of the 10th International Conference on Field Programmable Logic and Applications (FPL '2000, August 28--30, 2000).

``A Streaming Multi-Threaded Model.''
Eylon Caspi, Randy Huang, Yury Markovskiy, Joseph Yeh, John Wawrzynek, and André DeHon.
Presented at Third Workshop on Media and Stream Processors (MSP-3, December 2, 2001).

``Analysis of Quasi-Static Scheduling Techniques in a Virtualized Reconfigurable Machine.''
Yury Markovskiy, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, and André DeHon.
Published in Proceedings of the Tenth ACM International Symposium on Field-Programmable Gate Arrays (FPGA 2002, Feb. 24--26, 2002).

``SCORE: Stream Computations Organized for Reconfigurable Execution.''
Eylon Caspi, Randy Huang, Yury Markovskiy, Joseph Yeh, John Wawrzynek, and André DeHon.
Presented at the 2002 System on Chip Seminar (SoC 2002, November 20-21, 2002).

``Programming SCORE.''
Eylon Caspi.
Technical Report No. EECS-2005-25, EECS Department, University of California, Berkeley, 2005.

(Also see Michael Chu's masters thesis below)

(Also see Yury Markovskiy's masters thesis below)

(Also see Fast Routing papers below, to address online routing)

(Also see Eylon Caspi's Ph.D. thesis below

``The Garp Architecture and C Compiler.''
Timothy J. Callahan, John R. Hauser, and John Wawrzynek.
IEEE Computer, April 2000.

``Garp: A MIPS Processor with a Reconfigurable Coprocessor.''
John R. Hauser and John Wawrzynek.
Published in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97, April 16-18, 1997).

``The Garp Architecture.''
John R. Hauser.

(Also see John Hauser's Ph.D. thesis below)

``Instruction Level Parallelism for Reconfigurable Computing.''
Timothy J. Callahan and John Wawrzynek.
FPL'98, Field-Programmable Logic and Applications, 8th International Workshop, Tallinn, Estonia, September 1998. Published in Springer-Verlag LNCS 1482, Hartenstein and Keevallik eds.

``Adapting Software Pipelining for Reconfigurable Computing.''
Timothy J. Callahan and John Wawrzynek.
Published in Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'00, November 17-18, 2000).

``Fast Module Mapping and Placement for Datapaths in FPGAs.''
Timothy J. Callahan, Philip Chong, André DeHon, and John Wawrzynek.
Published in Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays (FPGA '98, February 22-24, 1998).

``Object Oriented Circuit-Generators in Java.''
Michael Chu, Nicholas Weaver, Kolja Sulimma, André DeHon, and John Wawrzynek.
Published in Proceedings of the International Symposium on Field-Programmable Gate Arrays for Custom Computing Machines (FCCM '98, April 15-17, 1998).

``Reconfigurable Computing: What, Why, and Design Automation Requirements? .''
André DeHon and John Wawrzynek.
Published in Proceedings of the 1999 Design Automation Conference (DAC '99, June 21-25, 1999).

``Hardware-Assisted Fast Routing.''
André DeHon, Randy Huang, and John Wawrzynek.
Published in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '02, April 22--24, 2002).

``Stochastic, Spatial Routing for Hypergraphs, Trees, and Meshes.''
Randy Huang, John Wawrzynek, and André DeHon.
Published in Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA '03, February 23--25, 2003).

``Post Placement C-slow Retiming for the Xilinx Virtex FPGA.''
Nicholas Weaver, Yury Markovskiy, Yatish Patel, and John Wawrzynek.
Published in Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA '03, February 23--25, 2003).

``Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why you don't really want 100% LUT utilization).''
André DeHon.
Published in Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays (FPGA '99, February 21-23, 1999).

``HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array.''
William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, Varghese George, John Wawrzynek, and André DeHon.
Published in Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays (FPGA '99, February 21-23, 1999).

``Embedded DRAM for a Reconfigurable Array.''
Stylianos Perissakis, Yangsung Joo, Jinhong Ahn, André DeHon, and John Wawrzynek.
Published in Proceedings of the 1999 Symposium on VLSI Circuits (VLSI '99, June 17-19, 1999).

``Balancing Computation and Memory in High Capacity Reconfigurable Arrays.''
Stylianos Perissakis.
Ph.D. Thesis, May 2000.

``Augmenting a Microprocessor with Reconfigurable Hardware.''
John Reid Hauser.
Ph.D. Thesis, December 2000.

``Dynamic Runtime Scheduler Support for SCORE.''
Michael Monkang Chu.
Masters Thesis, December 2000.

``Automatic Compilation of C for Hybrid Recofigurable Architectures.''
Timothy John Callahan.
Ph.D. Thesis, December 2002 (filed July 2002).

``Quasi-Static Scheduling for SCORE.''
Yury Markovskiy.
Masters Thesis, December 2004.

``Design Automation for Streaming Systems.''
Eylon Caspi.
Ph.D. Thesis, December 2005.