Integrating Processors and Reconfigurable Logic

Several research efforts have begun to look at the issues associated with coupling processors and reconfigurable logic on a single die. On this page, we collect pointers into the various efforts.

• PRISM -- PRISM is, perhaps, the earliest work looking directly at Processor and FPGA cooperation on computing tasks. Peter Athanas' thesis deals with compilation for mixed architectures and touches briefly on integration options.
• DPGA-coupled Microprocessors -- André DeHon's FCCM'94 paper [PS] [HTML] is one early description of the concept along with the motivation for coupling the two units -- but the paper is weak on details and costs. A later technical report [PS] [HTML] catalogs architectural options for integration. His more recent work (e.g. [TR blurb]) has begun to quantify some of the areas and costs which were missing from the earliest work.
• PRISC -- Razdan and Smith developed a system to automatically extract code for an integrated reconfigurable accelerator from conventional processor executables. [Razdan Thesis Abstract] [Razdan Thesis] [Micro'94] [ICCD'94]
• Cypris Crypto Processor -- Lockheed Martin/NSA developed an encryption processor [may need netscape to view properly] which features an integrated PLA structure for high-speed, programmable, cryptographic applications.
• OneChip -- Ralph Wittig developed a detailed architecture for such an integrated systems and explored a number of application examples. [OneChip documentation] Paul Chow and Jeff Jacob continue to evolve that architecture. The most notable addition is memory address scoreboarding to support blocked memory to memory operations. [Jacob 98 Thesis PS]
• Garp -- Garp is a microprocessor core with a programmable gate array coprocessor, integrated on the same chip under development at UC Berkeley. [architecture] [compilation]
• Chimaera -- Chimaera is a reconfigurable functional unit in the spirit of the PRISC reconfigurable PFU, under develpment at Northwestern. [overview and paper links]
• NAPA -- NAPA couples National Semiconductor's CLAy array with a RISC processor core for use in embedded signal processing applications. [National Semiconductor ACS Web Page]
• Triscend E5 -- reconfigurable cells with a microcontroller to provide customizable peripherals and interfacing. [Triscend E5 Docs] A recent announcement indicates an ARM-based reconfigurable processor is in the works.
• Modeling -- Albaharna Osama has a series of papers [ISCAS'94] [ICCD'94] [FCCM'96] modeling the area-time costs/benefits for processors and reconfigurable architectures. [email <a.osama@ic.ac.uk>]
• RISC+FPGA case study -- Pramod Viswanath and Sriram Rajamani did a quantitative case study on the effects of several processor-reconfigurable array interface issues. [Project Report Page]

To see this in context, see the relevant lecture slides from CS294-6: Reconfigurable Computing:

• Part I [PowerPoint] [2up PostScript]
• Part II [PowerPoint] [2up PostScript]

This summary is intentionally limited to systems which tightly couple the processor and the reconfigurable array resources -- mostly focusing on cases where the two are integrated on the same die.

See Steve Guccione's list of FPGA-based Computing Machines, for a more general collection of FPGA-based computing computing machines.

See Scott Hauck's ``The Roles of FPGAs in Reprogrammable Systems'' for an in depth review of many, contemporary, multi-FPGA systems.

• Gerald Estrin -- FIXED + VARIABLE computer [IEEE Trans. on Electronic Computers, v12, p747-754,755-773, 1963] [Proc. of the Wester Joint Computer Conference, p. 33, 1960]. A scanned copy of one of the original technical reports is available from UCLA.
• Mario Schaffner [IEEE Trans. on Computers, v27, n12, p1015-1028, 1978]