A missing piece in existing reconfigurable hardware is a well defined ``architecture'' and compute model that provides a consistent view of the machine, regardless of implementation details, including number and composition of physical resources. The challenge is to find the right computational abstractions to characterize the family of reconfigurable devices we can envision, expose a uniform view to the programmer, and represent the computation in a manner which a wide-range of hardware implementations can exploit efficiently. The BRASS project is developing a stream-oriented computational model to address this issue, providing an abstract view of the reconfigurable hardware, which exposes its strengths while abstracting the actual composition of physical resources. We call this stream-oriented computational model SCORE. The key concept in this model is that a computation is broken up into compute pages. Compute pages are linked together in a data-flow manner with streams. A run-time OS manager allocates and schedules pages at run-time for both for computations and memory.