and André DeHon.
Presented at Third Workshop on Media and Stream Processors (MSP-3, December 2, 2001),
in conjunction with The 34th International Symposium on Microarchitecture (MICRO-34, Austin, Texas, December 1--5, 2001).
Abstract: We present SCORE (Stream Computations Organized for Reconfigurable Execution), a multi-threaded model that relies on streams to expose thread parallelism and to enable efficient scheduling, low-overhead communication, and scalability. We present work to-date on SCORE for scalable reconfigurable logic, as well as implementation ideas for SCORE for processor architectures. We demonstrate that streams can be exposed as a clean architectural feature that supports forward compatibility to larger, more parallel hardware.