BRASS Research Group

Embedded DRAM for a Reconfigurable Array

Article by Stylianos Perissakis, Yangsung Joo, Jinhong Ahn, André DeHon, and John Wawrzynek published in Proceedings of the 1999 Symposium on VLSI Circuits (VLSI '99, June 17-19, 1999), 4 pages.

Abstract: A field-programmable gate array, coupled with an on-chip 2 Mb DRAM bank has been designed, to aid in the study of the tradeoffs involved in the design of embedded DRAMs for FPGAs. The memory can be used both as configuration storage, enabling configuration in under 5 usec, and application data memory, providing application logic executing on the array with up to 2 GB/sec data bandwidth. The variable latency of the DRAM is hidden from the logic by a stall mechanism and an SRAM-like interface.


Talk Slides

[BRASS Home] [Projects] [Class] [Documents] [People] [Contact] [Sponsors] [Links]