BRASS Research Group

Instruction Level Parallelism
for Reconfigurable Computing

Article by Timothy J. Callahan and John Wawrzynek, FPL'98, Tallinn, Estonia, September 1998. Published in Springer-Verlag LNCS 1482, Hartenstein and Keevallik eds.


Reconfigurable coprocessors can exploit large degrees of instruction-level parallelism (ILP). In compiling for reconfigurable coprocessors, we have found it convenient to borrow techniques previously developed for exploiting ILP for very long instruction word (VLIW) processors, specifically, hyperblock formation and scheduling. With some minor adaptations, these techniques are a natural match for automatic compilation to a reconfigurable coprocessor. This paper reviews these techniques in their original context, describes how we have adapted them for reconfigurable computing, and presents some preliminary results on compiling actual application programs written in the ANSI C programming language.


The proceedings for the FPL'98 conference are available as part of the
Springer Lecture Notes in Computer Science Series.

Note that another boost in ILP is achieved through pipelined execution as described in this subsequent paper.
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