Article by William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, Varghese George, John Wawrzynek, and André DeHon published in Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays (FPGA '99, February 21-23, 1999), 10 pages.
Abstract: There is no inherent characteristic forcing Field Programmable Gate Array (FPGA) or Reconfigurable Computing (RC) Array cycle times to be greater than processors in the same process. Modern FPGAs seldom achieve application clock rates close to their processor cousins because (1) resources in the FPGAs are not balanced appropriately for high-speed operation, (2) FPGA CAD does not automatically provide the requisite transforms to support this operation, and (3) interconnect delays can be large and vary almost continuously, complicating high frequency mapping. We introduce a novel reconfigurable computing array, the High-Speed, Hierarchical Synchronous Reconfigurable Array (HSRA), and its supporting tools. This package demonstrates that computing arrays can achieve efficient, high-speed operation. We have designed and implemented a prototype component in a 0.4um logic design on a DRAM process which will support 250MHz operation for CAD mapped designs.
Copyright 1999 ACM, Inc.Paper
hsra_fpga99.pdf [3.1 MB].
hsra_fpga99.ps.gz [72 kB].
hsra_fpga99.ps.Z [137 kB].
hsra_fpga99.ps [422kB].
Talk Slides
hsra_talk_fpga99.ppt [314 kB].
hsra_talk2up_fpga99.ps [2.8 MB].
Poster Slides
hsra_poster_fpga99.ppt
[548 kB].
hsra_poster2up_fpga99.ps [3.9 MB].